In an SRAM cell 10 shown in FIG. 1, each bit is stored on four transistors M1, M2, M3, M4 that form two cross-coupled inverters. SRAM cell 10 has two stable states which are used to denote ‘0’ and ‘1’. Two additional access transistors M5, M6 serve to control the access to each SRAM cell 10 during read and write operations. Thus, it typically takes six transistors to store one memory bit.
Access to the SRAM cell 10 is enabled by a word line WL which controls the two access transistors M5, M6 which, in turn, control whether the cell 10 should be connected to the bit lines BL and BL′. The bit lines BL and BL′ are used to transfer data for both read and write operations. While it is not strictly necessary to have two bit lines, both the signal and the inverse are typically provided since it improves noise margins.
If the word line WL is not asserted, the access transistors M5, M6 disconnect the cell 10 from the bit lines BL and BL′. If the cell 10 is disconnected, the two cross-coupled inverters continue to reinforce each other as long as they remain disconnected.
In order to read the cell 10, both bit lines BL and BL′ are pre-charged to the same voltage before the word line WL connects the bit lines BL and BL′ to the cell 10. By observing which bit line discharges to ground allows identifying whether a ‘0’ or a ‘1’ is stored in the cell 10.
In order to write the cell 10, two different voltages (i.e. ground and a voltage different from ground) are applied on the bit lines BL and BL′ by a write circuit that is connected with the bit lines BL and BL′ via its gate. Depending on which of the two bit lines BL and BL′ is at ground and which of them is at the other voltage a ‘0’ or a ‘1’ is written to the cell 10.
Thereby, typical SRAM designs use the core logic voltage (Vdd) for the SRAM arrays including the SRAM cells (i.e. for the voltage different from ground).
Due to the loss of cell stability in recent technologies caused by low voltages, threshold voltage (Vt) scatter, increased relative variations and the like, an additional array cell specific voltage (Vcs) has been introduced to increase cell stability. While only the cell 10 is connected to this special voltage (Vcs), the word line WL, the bit line and also the write circuit remain at the lower voltage (Vdd). Due to this, (Vdd) is also known as bit line voltage. Doing so reduces the stress to the cell 10 during the read access and improves stability. In general, as a rule of thumb stability improves while the difference between the cell voltage (Vcs) and the bit line voltage (Vdd) grows.
On the other side for write, the cell 10 at the higher voltage (Vcs) needs to be overwritten with the lower voltage (Vdd). Thereby only a small corridor, further called operating window 20, remains where the array operates properly as shown in FIG. 2. This operating window 20 is represented by the region A in FIG. 2. It can be seen that this region is limited at Vdd/V≈0.9. To improve writeability, it is also known to connect the word line WL to (Vcs), but the limited operating window 20 still remains. Since both power supplies for (Vcs) and (Vdd) are independent from each other, in a worst-case scenario this operating window 20 is further reduced due to independent variations of the two voltages, caused by varying power supply, package and chip power distribution and the like, making it difficult to control. Ideally, (Vcs) has to track with (Vdd) to stay in the center of the operating window 20.
Alternatively, complex schemes have been proposed to switch between the two voltages, wherein (Vdd) is used for write and (Vcs) is used for read operations. A drawback of this solution is that a dummy cycle always needs to be introduced to switch between the two operations. Also the power consumption for write operations increases since the overall voltage level at the bit lines is increased which is driving the overall power consumption of the array.